A significant challenge in integrated circuits (ICs) is clock and data recovery (CDR). In order for one IC (the transmitter) to talk to another (the receiver), their clocks must be aligned, so that data can be received. A circuit structure called an interpolator is typically used to adjust the phase of the clock in the receiver. To achieve good performance from the interpolator, the edge rate of the incoming oscillator (OSC) must be carefully controlled. An edge rate controller (ERC) provides this functionality. Slow edges from the ERC provide the interpolator with more linear inputs, which improves the overall linearity of the interpolator and increases stability of the CDR loop. Slower edges from the ERC are also more susceptible to process, voltage and temperature (PVT) variation. If the edges become too slow, the interpolator stops functioning. Thus, the edge rate of the ERC must be carefully controlled and monitored.